The present invention relates to a voltage-controlled oscillator (VCO), and, more particularly, to a ring type voltage-controlled oscillator which uses a plurality of differential delay cells and which is used to generate a high-frequency clock signal for the internal circuits of an LSI, such as a micro computer (MCU: Micro Control Unit) or a digital signal processor (DSP). This voltage-controlled oscillator is adapted to various applications to improve the processing performance of an LSI and suppress the overall power of a system by using a low-frequency clock for an external clock of the LSI and a high-frequency clock for an internal clock of the LSI.
FIG. 1 shows a conventional fundamental voltage-controlled oscillator which uses a plurality of differential delay cells. This oscillator includes a level converting circuit and amplitude controller 1, differential delay cells 2 to 6, which constitute a voltage-controlled oscillation section 100, and an output level converting circuit 7. The delay cells 2 to 6 have the same circuit structure which comprises PMOS (P channel MOS) transistors P1 and P2 and NMOS (N channel MOS) transistors N1 to N3. The voltage-controlled oscillator performs its oscillating operation as the differential output signals of the first-stage delay cell 2 are sequentially supplied to the subsequent stages of delay cells 3, 4 and 5 and the differential output signals, Vip and Vim, of the last-stage delay cell 6 are supplied to the output level converting circuit 7 and are fed back to the gates of the NMOS transistors N2 and N1 in the first-stage delay cell 2. An amplitude control voltage Vbp output from the level converting circuit and amplitude controller 1 is supplied to the gates of the PMOS transistors P1 and P2 in each of the delay cells 2-6, and a control voltage Vcn output from the level converting circuit and amplitude controller 1 is supplied to the gate of the NMOS transistor N3, thereby controlling the oscillating operation. The output level converting circuit 7 outputs a clock signal CKout. Note that the level converting circuit and amplitude controller 1, the delay cells 2-6 and the output level converting circuit 7 operate on power supply voltages VDD and VSS.
FIG. 2 exemplifies the structure of a level converting circuit 1A in the circuit shown in FIG. 1, FIG. 3 exemplifies the structure of an amplitude controller 1B in the circuit shown in FIG. 1 and FIG. 4 exemplifies the structure of the output level converting circuit 7 in the circuit shown in FIG. 1.
As shown in FIG. 2, the level converting circuit 1A comprises PMOS transistors P3 and P4, NMOS transistors N4 and N5 and a resistor R1. This circuit 1A performs voltage/current conversion of a control voltage Vin input externally and then performs current/voltage conversion to generate the control voltage Vcn. The control voltage Vin is supplied to the gate of the NMOS transistor N4 and the control voltage Vcn is output from a common node between the drains of the PMOS transistor P4 and the NMOS transistor N5.
The amplitude controller 1B shown in FIG. 3 comprises a reference voltage generator 8, an operational amplifier 9 and an amplitude-control target circuit 101. The amplitude-control target circuit 101 comprises PMOS transistors P5 and P6 and NMOS transistors N6 to N8. A reference voltage Vref output from the reference voltage generator 8 is supplied to the inverting input terminal (-) of the operational amplifier 9 and the gate of the NMOS transistor N7. The control voltage Vcn that is output from the level converting circuit 1A is supplied to the gate of the NMOS transistor N8. The output of the operational amplifier 9 is supplied to the gates of the PMOS transistors P5 and P6 and is output as the amplitude control voltage Vbp.
As shown in FIG. 4, the output level converting circuit 7 comprises PMOS transistors P7 to P9 and NMOS transistors N9 to N12. The output signal Vim of the delay cell 6 is supplied to the gate of the NMOS transistor N9, and the output signal Vip to the gate of the NMOS transistor N10. The clock signal CKout is acquired from a common node between the drains of the PMOS transistor P9 and the NMOS transistor N12.
With the above structure, the control voltage Vin is input to the level converting circuit 1A where it is converted to the control voltage Vcn according to a control current Icnt of the delay cells 2-6. In the amplitude controller 1B, the amplitude-control target circuit 101 has the same structure as the delay cells 2-6 and the supply voltage VDD is applied to one input terminal (the gate of the NMOS transistor N6) of the amplitude-control target circuit 101 while the reference voltage Vref generated by the reference voltage generator 8 is applied to the other input terminal (the gate of the NMOS transistor N7). An output voltage from an output terminal 102 of the amplitude-control target circuit 101 on that side where the power supply voltage VDD is input and the reference voltage Vref generated by the reference voltage generator 8 are respectively input to the non-inverting input terminal (+) and the inverting input terminal (-) of the operational amplifier 9 whose output is sent out as the amplitude control voltage Vbp. As this amplitude control voltage Vbp is applied to the gates of the PMOS transistors P5 and P6 in the amplitude-control target circuit 101, feedback control is carried out to make the output voltage from the output terminal 102 equal to the reference voltage Vref generated by the reference voltage generator 8. This indicates that as the amplitude control voltage Vbp is input to the voltage-controlled oscillation section 100 comprising the delay cells 2-6 which have the same circuit structure as that of the amplitude-control target circuit 101, the output voltage output from the output terminal of the voltage-controlled oscillation section 100 becomes the same as the reference voltage Vref generated by the reference voltage generator 8 when the voltage at one input terminal of each of the delay cells 2-6 has the level of the power supply voltage VDD.
Therefore, the amplitude of the oscillation waveform of this voltage-controlled oscillation section 100 is always kept constant by the amplitude control voltage Vbp so that the maximum value of the oscillation waveform becomes the power supply voltage VDD and the minimum value becomes the reference voltage Vref generated by the reference voltage generator 8.
Further, as the control voltage Vcn which controls the oscillation frequency of the voltage-controlled oscillation section 100 is also input to the amplitude-control target circuit 101, the amplitude control voltage Vbp changes in accordance with a change in control voltage Vcn. Even if the oscillation frequency of the voltage-controlled oscillation section 100 changes, therefore, the amplitude of the oscillation waveform of the voltage-controlled oscillation section 100 is always kept constant by the amplitude control voltage Vbp so that the maximum value of the oscillation waveform becomes the power supply voltage VDD and the minimum value becomes the reference voltage Vref generated by the reference voltage generator 8. As a result, the oscillation output as shown in FIG. 5 is acquired. FIG. 5 shows the oscillation waveform of the voltage-controlled oscillation section 100 which comprises small-amplitude differential delay cells whose output amplitude is controlled to the level of the power supply voltage VDD from the level of the reference voltage Vref.
As apparent from the above, the small-amplitude output of the voltage-controlled oscillation section 100 is supplied to the output level converting circuit 7 where its level is converted to the CMOS level of the power supply voltage VDD from the level of the ground voltage VSS that is used in a CMOS logic circuit, and the resultant signal is output as the clock signal CKout.
The use of the above-described differential delay cells is advantageous in two features of the delay cells. One is that the delay cells insusceptible to common-mode noise, such as noise in the voltage supply, and the other is that the delay cells are suitable for a high-frequency operation.
The insusceptibility to noise is regarded as one of important circuit techniques for analog circuits which are invulnerable to digital noise that is generated in a digital circuit in the mixed signalization (mixed integration of an analog circuit and a digital circuit on the same chip) in the recent large scale integrated circuits (LSIs). As microfabrication or the like of devices makes the gate delay of transistors smaller, there is a tendency of using a high-frequency clock for the internal clock of an LSI in order to enhance the signal processing performance of the LSI. The second feature, the suitability for a high-frequency operation, is therefore convenient to that recent tendency. In this respect, a voltage-controlled oscillator which generates this internal clock is demanded to have a high oscillation frequency.
The oscillation frequency, fosc, of a voltage-controlled oscillator is given by EQU fosc=1/(N.times.Tdelay)
where N is the number of stages of delay cells and Tdelay is the delay time per delay-cell stage.
The delay time Tdelay is given by EQU Tdelay=Co.times.Vo/Icnt
where Co is the output load capacitance of a delay cell, Vo is the output amplitude of the delay cell and Icnt is the control current which controls the delay time of the delay cell.
The oscillation frequency of the voltage-controlled oscillation section 100 can be increased by reducing the number of stages N of delay cells or shortening the delay time Tdelay per delay-cell stage. If the number of stages N of delay cells is small, a variation in delay time from one delay-cell stage to another may directly affect the oscillation frequency that is produced in the voltage-controlled oscillation section 100. Reducing the number of stages N of delay cells is not deemed very preferable from the viewpoint of the stability of the oscillation frequency produced in the voltage-controlled oscillation section 100.
The output load capacitance Co of a delay cell is the gate capacitance of the input transistor of the next stage of a delay cell and is a parameter which depends on the miniaturization of processes. The maximum value of the control current Icnt for controlling the delay time of a delay cell depends on the size of transistors in use, so that increasing the size of the transistors to increase the control current Icnt makes the output load capacitance Co of the delay cell higher. Therefore, the control current Icnt that controls the delay time of a delay cell seems to have an optimal value according to the process miniaturization.
From the above, circuit-based schemes which can increase the oscillation frequency of the voltage-controlled oscillation section 100 without depending on the process miniaturization are the reduction in the number of delay-cell stages N and the lowering the output amplitude Vo of delay cells.
While lowering the output amplitude Vo of delay cells is effective in increasing the oscillation frequency of the voltage-controlled oscillation section 100, it reduces the S/N ratio, which requires the use of differential delay cells to enhance the performance to noise. It is also necessary to keep the output amplitude of the voltage-controlled oscillation section 100 constant as well as keep the center voltage (the voltage at which the non-inverted output and the inverted output cross each other) constant in consideration of the operational characteristics of the output level converting circuit 7 which converts the level of the small-amplitude output of the voltage-controlled oscillation section 100 to the CMOS level.
If the output amplitude and the center voltage of the voltage-controlled oscillation section 100 are not kept constant, the proper operation of the output level converting circuit 7 which converts the level of the small-amplitude output of the voltage-controlled oscillation section 100 to the CMOS level becomes difficult, thus impairing the stability of the duty and frequency of the clock signal CKout output from the output level converting circuit 7. Further, the output level converting circuit 7 may become inoperable so that the clock signal CKout cannot be output.
The amplitude controller 1B as shown in FIG. 3 whose amplitude-control target circuit 101 uses the same circuit structure as the delay cells that constitute the voltage-controlled oscillation section 100 works effectively to some extent to ensure the proper operation of the output level converting circuit 7 which converts the level of the small-amplitude output of the voltage-controlled oscillation section 100 to the CMOS level. While the voltage-controlled oscillation section 100 and the amplitude controller 1B use the same delay cells, the following problem arises due to the difference in operational state between them.
Because of the nature of the oscillating operation, the voltage-controlled oscillation section 100 always performs an AC operation in which an "H" level (the level of the power supply voltage VDD) and an "L" level (the level of the reference voltage Vref) repeat alternately. By way of contrast, the amplitude controller 1B performs a DC operation in which the input voltages are always fixed to the "H" level (the level of the power supply voltage VDD) and the "L" level (the level of the reference voltage Vref). The difference in operational state between the AC operation and the DC operation is negligible when the oscillation frequency of the voltage-controlled oscillation section 100 is low, but becomes prominent as this oscillation frequency gets higher. When the oscillation frequency of the voltage-controlled oscillation section 100 is low, the time in which the oscillation frequency is stable at the "H" level and the "L" level is long as shown in FIG. 6A, so that "H" level and the "L" level reach the desired levels to ensure the stable operation as done in the amplitude controller 1B. As the oscillation frequency of the voltage-controlled oscillation section 100 becomes higher, however, the time in which the oscillation frequency is stable at the "H" level and the "L" level becomes shorter as shown in FIG. 6B. This raises such a problem that the operation goes to the next cycle before the output amplitude reaches the desired level, thus making the output amplitude lower (the lower limit Vbottom of the output amplitude becoming higher than the reference voltage Vref) or such a problem that the level of the center voltage of the output amplitude varies.
Those two problems degrade the linearity of the conversion characteristics of the voltage and frequency of the voltage-controlled oscillation section 100 and make difficult the proper operation of the output level converting circuit 7 which converts the level of the small-amplitude output of the voltage-controlled oscillation section 100 to the CMOS level. This deteriorates the stability of the duty and frequency of the clock signal CKout output from the output level converting circuit 7. Further, the output level converting circuit 7 may become disabled so that the clock signal CKout cannot be output. The disabling of the output of the clock signal CKout is critical because it disables the feedback control in a PLL (Phase Locked Loop) circuit and puts the PLL circuit in an unrecoverable state.
Therefore, the prior art needs to take some design measures, such as a design which does not make the oscillation frequency of the voltage-controlled oscillation section 100 higher by increasing the number of stages of delay cells of the voltage-controlled oscillation section 100. From the view point of application, the conventional voltage-controlled oscillator cannot be used in a high-frequency range and thus suffers a narrow frequency range, which limits the range of application systems and puts restrictions on the usage of the voltage-controlled oscillator.